Solution:
88 10001000
+ 93 10010011
11B 00011011
CY = 1 since there is a carry beyond the D7 bit
AC = 0 since there is no carry from the D3 to the D4 bi
P = 0 since the accumulator has an even number of 1s (it has four 1s)

REGISTER
BANKS AND
STACK
RAM Memory
Space
Allocation
􀂉 There are 128 bytes of RAM in the
8051
􀂾 Assigned addresses 00 to 7FH
􀂉 The 128 bytes are divided into three
different groups as follows:
1) A total of 32 bytes from locations 00 to
1F hex are set aside for register banks
and the stack
2) A total of 16 bytes from locations 20H to
2FH are set aside for bit-addressable
read/write memory
3) A total of 80 bytes from locations 30H to
7FH are used for read and write storage,
called scratch pad

8051
REGISTER
BANKS AND
STACK
RAM Memory
Space
Allocation
(cont’)
Scratch pad RAM
Bit-Addressable RAM
Register Bank 3
Register Bank 2
Register Bank 1 (stack)
Register Bank 0
00
07
08
0F
10
17
18
1F
20
2F
30
7F
RAM Allocation in 8051

8051
REGISTER
BANKS AND
STACK
Register Banks
􀂉 These 32 bytes are divided into 4
banks of registers in which each bank
has 8 registers, R0-R7
􀂾 RAM location from 0 to 7 are set aside for
bank 0 of R0-R7 where R0 is RAM location
0, R1 is RAM location 1, R2 is RAM
location 2, and so on, until memory
location 7 which belongs to R7 of bank 0
􀂾 It is much easier to refer to these RAM
locations with names such as R0, R1, and
so on, than by their memory locations
􀂉 Register bank 0 is the default when
8051 is powered up

8051
REGISTER
BANKS AND
STACK
Register Banks
(cont’)
R7
R6
R5
R4
R3
R2
R1
R0
Bank 0 Bank 1 Bank 2 Bank 3
7 R8
6 R7
5 R6
4 R5
3 R4
2 R2
0  R0
 1 R1
F R7
E R6
D R5
C R4
B R3
A R2
8 R0
9 R1
1F R7
1E R6
1D R5
1C R4
1B R3
1A R2
18 R1
19 R0
17 R7
16 R6
15 R5
14 R4
13 R3
12 R2
10 R0
11 R1
Register banks and their RAM address

8051
REGISTER
BANKS AND
STACK
Register Banks
(cont’)
􀂉 We can switch to other banks by use
of the PSW register
􀂾 Bits D4 and D3 of the PSW are used to
select the desired register bank
􀂾 Use the bit-addressable instructions SETB
and CLR to access PSW.4 and PSW.3
PSW bank selection
Bank 3    1            1
Bank 2    1            0
Bank 1    0            1
Bank 0    0            0
RS 1(PSW.4)  RS0(PSW.3)


8051
REGISTER
BANKS AND
STACK
Register Banks
(cont’)
Example 2-5
MOV R0, #99H ;load R0 with 99H
MOV R1, #85H ;load R1 with 85H
Example 2-6
MOV 00, #99H ;RAM location 00H has 99H
MOV 01, #85H ;RAM location 01H has 85H
Example 2-7
SETB PSW.4 ;select bank 2
MOV R0, #99H ;RAM location 10H has 99H
MOV R1, #85H ;RAM location 11H has 85H

8051
REGISTER
BANKS AND
STACK
Stack
􀂉 The stack is a section of RAM used by
the CPU to store information
temporarily
􀂾 This information could be data or an
address
􀂉 The register used to access the stack
is called the SP (stack pointer) register
􀂾 The stack pointer in the 8051 is only 8 bit
wide, which means that it can take value
of 00 to FFH
􀂾 When the 8051 is powered up, the SP
register contains value 07
􀂃 RAM location 08 is the first location begin used
for the stack by the 8051
Department of Computer Science and Information Engineering

8051
REGISTER
BANKS AND
STACK
Stack
(cont’)
􀂉 The storing of a CPU register in the
stack is called a PUSH
􀂾 SP is pointing to the last used location of
the stack
􀂾 As we push data onto the stack, the SP is
incremented by one
􀂃 This is different from many microprocessors
􀂉 Loading the contents of the stack back
into a CPU register is called a POP
􀂾 With every pop, the top byte of the stack
is copied to the register specified by the
instruction and the stack pointer is
decremented once